This invention relates to a computer system having a sequence controller for accessing peripheral devices.
In many data processing systems, a common bus is used to link together a plurality of units to the system. The bus permits any two units linked to the system to communicate or transfer information between each other.
Typically, communication is established by any unit by making a request to the bus for a bus cycle. When that bus cycle is granted, the requesting unit becomes the master and may address any other unit, linked to the bus, as a slave.
Transfers requiring a response from a slave unit, such as a read memory transfer from the slave, require a response cycle. In these cases, the master indicates a response is required and identifies itself to the slave. When the required information becomes available, the slave will assume the role of the master and initiate a transfer of information to the requesting unit. Thus, with such an interchange, two bus cycles are required. During the time it takes the slave to respond, other units may use the bus to communicate with any other unit that does not involve the master-slave units above. In the event that two units request simultaneous service from the bus, tie-breaking logic may be included at each unit directly coupled to the bus.
A typical data processing system utilizing a common bus is shown in FIG. 1. As shown, a bus 100 which often comprises multiple lines, is coupled to a memory storage unit 102. The memory storage unit may comprise several memory storage units, each in communication with the bus. Also connected to this data processing system is a scientific-arithmetic unit 108 and three controllers: a basic device controller 110, a communications controller 112, and a mass store/magnetic tape controller 114. The basic controller 110 is coupled to the bus to allow multiple unit record peripheral devices 116 to have access to the bus 100. Using the basic controller in this manner avoids larger demands on the bus that would result if each unit record peripheral device had a direct access to the bus. Similarly, a communications controller 112, which is used to provide communication control via modem devices, and a mass store/magnetic tape controller 114, which is used to control mass storage devices such as a tape peripheral device 118 or a disk peripheral device 120, is in communication with the bus 100.
In addition to the above devices, a central processor 106 is connected to the bus for controlling the bus cycles and regulating data transferred over the bus. Thus, any one of these devices which are coupled to the bus 100 may address or communicate with any other unit connected to the bus 100. For example, the tape peripheral 118 may address the memory storage unit 102 by way of the controller 114.
To insure that the proper unit is addressed by a master unit, a channel number exists for every end point in the system with the exception of the memory type processing elements. In those cases, a channel number is assigned to each device along with the memory address identifying the end point. Some devices, such as a full duplex device, utilize two channel numbers. Others, such as an output only or an input only device, use only one channel each. Units with multiple inputs and outputs ports generally require a block of consecutive channel numbers to distinguish between the different ports.
With such a system, different priorities are established for accessing the bus. For example, when a peripheral has access to the bus via a controller, all other peripherals connected to this controller would be locked out or denied access to the bus.
Further details regarding the above type of bus system is disclosed in the following U.S. patents. The referenced patents pertain to the proprietary bus system of Honeywell.
(a) Data Processing System Providing Split-Bus Cycle Operation by Frank V. Cassarino, Jr. et al, issued Dec. 14, 1976, and having U.S. Pat. No. 3,997,896. PA1 (b) Data Processing System Providing Locked Operation of Shared Resources by George J. Barlow et al, issued Dec. 28, 1976, and having U.S. Pat. No. 4,000,485. PA1 (c) Data Processing System Having Distributed Priority Network by George J. Barlow, issued June 14, 1977, and having U.S. Pat. No. 4,030,075. PA1 (d) Data Processing System Having Distributed Priority Network with Logic for Deactivating Information Transfer Requests by George J. Barlow, issued June 20, 1978, and having U.S. Pat. No. 4,096,569. PA1 (e) Apparatus for Processing Data Transfer Requests in a Data Processing System by Frank V. Cassarino, Jr. et al, issued Nov. 23, 1976, and having U.S. Pat. No. 3,993,981. PA1 (f) Data Processing System Having a Data Integrity Technique by George J. Barlow, issued Nov. 30, 1976, and having U.S. Pat. No. 3,995,258.